Referring to FIGS. 1a to 1e, there are illustrated several kinds of thin film transistors as multiple carrier elements using thin films. FIGS. 1a and 1b show thin film transistors of the coplanar type wherein source and drain electrodes, an insulation layer and a gate electrode are formed over a semiconductor layer used as an active layer in an overlapped manner and in the same direction. FIGS. 1c and 1d show thin film transistors of the staggered type wherein source and drain electrodes and a gate electrode are formed at both surfaces of a semiconductor layer in opposite directions. On the other hand, FIG. 1e shows a thin film transistor of the inverted staggered type wherein an insulation layer and a semiconductor layer are formed over a gate electrode.
The material of the semiconductor layer may include CdS, CdSe, CdSSe and the like. Generally, the semiconductor layer is formed by using a method of sintering the above-mentioned materials in an inert gas atmosphere containing a proper inert gas or a small amount of oxygen at a temperature of 570.degree. C. to 600.degree. C., using a solvent of CCl.sub.2. Alternatively, the material of the semiconductor layer may include TeInSb, SnO.sub.2 and In.sub.2 O.sub.3.
The material of the insulation layer may include organic materials such as nitrocellulose, glyceryl monostearate and Q-rac (made by Transene Co., Inc.) and inorganic materials such as BaTiO.sub.3, SiO.sub.2 and silicate cement.
On the other hand, materials of electrodes may include an Au paste, Sn, a Sn-Ga alloy (5% to 10% Sn), and an In amalgam.
The present invention concerns the inverted staggered type from the above-mentioned thin film transistors. Now, a conventional inverted staggered type thin film transistor will be described, in conjunction with FIGS. 2a and 2f.
As shown in FIG. 2a, an insulating transparent substrate 1 is first prepared. Over the transparent substrate 1, a metal layer for a gate electrode is deposited which is in turn subjected to a patterning, to form a gate electrode 2.
On the exposed surfaces of transparent substrate 1 and gate electrode 2, an insulating layer 3 is formed to insulate the gate electrode 2, as shown in FIG. 2b. A semiconductor layer 4 as a channel layer is then formed on the insulating layer 3. On the semiconductor layer 4 is formed another semiconductor layer 5 of a predetermined conductivity type (n type or p type) doped with the same conductivity type impurity ions for reducing contact resistance between the source and drain electrode and the semiconductor layer 4. Thereafter, the semiconductor layers 4 and 5 are patterned so that unnecessary portions of their opposite side edges are removed, as shown in FIG. 2d. After patterning, side surfaces of the patterned semiconductor layers 4 and 5 are exposed.
Subsequently, a metal layer 6 for source and drain electrodes is formed on the resultant exposed surface, as shown in FIG. 2e. Together with the semiconductor layer 5, the metal layer 6 is then subjected to a patterning so that their portions disposed above the gate electrode 2 are removed, as shown in FIG. 2f. By the patterning, unnecessary portions of opposite side edges of the metal layer 6 are also removed. At this time, opposite side edges of the semiconductor layers 4 and 5 are still covered with the metal layer 6. Thus, a through hole region 7, source and drain electrodes 6a and 6b are formed above the semiconductor layer 4.
Finally, an insulation layer 8 for a passivation is formed on the resultant exposed surfaces of the source and drain electrode 6a and 6b and the portion of semiconductor layer 4 corresponding to the through hole region 7.
The operation of the obtained conventional inverted staggered type thin film transistor shown in FIG. 2f will now be described.
As a voltage of about +10 V is applied to the gate electrode 2, electrons are generated at a boundary surfaces between the insulation layer 3 and the semiconductor layer 4 disposed on the insulation layer 3, so that a channel is formed at the semiconductor layer 4. At this time, an application of voltage of about +10 V between the source and drain electrodes 6a and 6b causes a current to flow through the channel. The current flows from the source electrode 6a, via the semiconductor layer 5, the boundary surfaces between the semiconductor layer 4 and the insulating layer 3 and then the semiconductor layer 5, to the drain electrode 6b.
However, the thin film transistor obtained by the conventional method has the following problems.
The source and drain electrodes are in contact with the semiconductor layer as the channel at their large portions, as shown in FIG. 3a. As a result, a vertical series resistance Rs of the semiconductor layer 4 is very large at sides of source and drain electrodes, as compared with contact resistances generated between semiconductor layers 4 and 5 and between the semiconductor layer 5 and the source and drain electrodes 6a and 6b. Otherwise, the value of channel conductance is decreased, so that a voltage drop is generated in the channel. Consequently, a voltage lower than the actually applied voltage is present between source and drain electrodes, resulting in a degradation in operational characteristic of the thin film transistor.